In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (“SDRAMs”), synchronous static random access memories (“SSRAMs”), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device are typically synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” refers to signals and operations outside of the memory device, and “internal” refers to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. However, with higher frequency clock signals, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result of inherent delays, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches. Additionally, as the frequency of the external clock increases, variations in the duty cycle of the clock signal introduce a greater duty cycle error. An ideal duty cycle for a clock signal is typically 50 percent. That is, over the period of a clock cycle, the clock signal is HIGH for 50 percent of the period. As the period of the clock signals become shorter due to the increased clock frequency, a clock variation that results in a subtle shift in duty cycle, and which can be ignored at a lower clock frequency, may result in a much more significant shift in the duty cycle of the higher frequency clock signal. In such instances, if the duty cycle of the clock signal is left uncorrected, timing errors may cause the memory device to fail.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay locked loops (“DLLs”) with duty cycle correction (“DCC”) circuits, as will be appreciated by those skilled in the art. Examples of DLLs with duty cycle correction are described in U.S. Pat. No. 7,227,809, issued Jun. 5, 2007, entitled “Clock generator having a delay-locked loop and duty cycle correction circuit in a parallel configuration,” naming Jongtae Kwak as inventor.
FIG. 1 illustrates a conventional DLL 110 and DCC circuit 120. The DLL includes an input buffer 202 that provides a buffered clock signal CLKBUF in response to receiving the CLK signal. The CLKBUF signal is delayed relative to the CLK signal due to a propagation delay of the input buffer 202. The CLKBUF signal is provided to a variable delay circuit 204 that has a variable delay controlled by an adjustment signal DADJ1 generated by a shift register 206. The output clock signal of the variable delay circuit 204 is the CLK0 signal, which is delayed relative to the CLKBUF signal by the variable delay. An output clock signal CLKSYNC is fed back through a model delay 208 to provide a feedback clock signal CLKFB1. The model delay 208 adds a delay to the CLKSYNC signal, which is approximately equal to the total delay of the input buffer 202, an output buffer 240 in the DCC 120, and the delay that is injected by the DCC circuit 120 to the CLK0 signal and a CLK180 signal. A phase detector compares the CLKBUF and CLKFB1 signals, and generates a control signal DCONT1 for the shift register 206 in response to the phase difference between the CLKBUF and CLKFB1 signals. The variable delay circuit 204 is adjusted until the variable delay is sufficient to synchronize the CLKBUF and CLKFB1 signals. When the CLKBUF and CLKFB1 signals are in phase, the DLL 110 is said to be “locked.” Under this condition, the timing of the CLK0 signal is such that the delay of the output buffer 240 is accommodated, and a clock signal output by the output buffer 240 would be in phase with the CLK signal.
The CLK0 signal is provided to the DCC circuit 120 for duty cycle correction. The DCC circuit 120 includes a first variable delay 230 and a second variable delay 232, which are coupled in series. An output clock signal CLKFB2 of the variable delay 232 is compared with the CLK0 signal by a phase detector 238. The phase detector 238 generates a control signal DCONT2 that is provided to a shift register 234. The shift register 234 generates an adjustment signal DADJ2 based on the DCONT2 signal that is used to adjust both the variable delay 230 and the variable delay 232 to the same delay. When the variable delays 230, 232 have been adjusted so that the phase difference between the CLK0 and CLKFB2 signals is an odd multiple of the clock period of the CLK0 signal an output clock signal CLK180 from the first variable delay 230 is 180 degrees out of phase from the CLK0 signal. As known in the art, the delay of the feedback loop for the DCC circuit 120, which is generally defined by the variable delays 230 and 232, is equal to one period of the CLK0 signal. Thus, one-half the loop delay, that is, the delay of one of the variable delays 230 or 232, will provide a delay equal to one-half the period of the CLK0 signal, which is a clock signal 180 degrees out of phase from the CLK0 signal. The CLK0 and CLK180 signals are used by the output buffer 240 to generate the CLKSYNC signal, which is synchronized with the CLK signal and has a corrected duty cycle.
The conventional clock generator 100 shown in FIG. 1 places the DLL 110 and DCC circuit 120 in series with each other. This arrangement requires a clock signal to propagate through a plurality of adjustable delay lines, each of which have an adjustable delay that is potentially affected by such factors as the consumption of power or space, and by the operating limitations of the circuit.
Although the conventional clock generator 100 can successfully generate a synchronized clock signal having a 50% duty cycle, the conventional arrangement of the DLL 110 and the DCC circuit 120 is susceptible to several issues. One issue is clock jitter. Clock jitter is exhibited as small variations in the phase of the output clock signal that is generated by the clock generator 100. Clock jitter can be caused by small fluctuations or variations in the delay times of the delay stages found in adjustable delay lines, such as in the DLL 110 and the DCC circuit 120. As the delay times of the delay stages fluctuate, the resulting clock signal will drift or “jitter.” The fluctuations in delay time can be caused by power supply noise, which affects the delay time of each active delay stages of an adjustable delay line. In a conventional arrangement of the DLL 110 and the DCC circuit 120, such as that shown in FIG. 1, having multiple adjustable delay lines (such as adjustable delay lines 204, 230, 232) coupled in series can compound a clock jitter problem. That is, a clock signal output by a first adjustable delay line will have clock jitter, and is propagated through a second adjustable delay line, which also injects jitter. The resulting clock signal output by the second adjustable delay line will have a cumulative clock jitter from both the first and second delay lines. Propagating the clock signal through one more adjustable delay line will only result in generating a clock signal having yet more clock jitter.
Other issues with the arrangement of the DLL 110 and the DCC circuit 120 of the clock generator 100 are slowness of operation and cumbersome size. The conventional clock generator 100 is slow because two different feedback loops must be locked in sequence before an acceptable CLKSYNC signal is generated. That is, in one arrangement, upon start up, the DCC 120 is synchronized before the DLL 110 is activated to provide a clock signal having the appropriate delay relative to the CLK signal. Alternatively, the DLL 110 is locked to generate a synchronized clock signal before the DCC 120 is activated for duty cycle correction. It may take the DLL 110 by itself several hundred clock cycles to obtain lock and generate a synchronized CLK0 signal. The DCC circuit 120 then takes additional time to adjust the variable delays 230 and 234 to synchronize the CLK0 signal and the CLKFB signal to provide a suitable CLK180 signal. The time for the DCC circuit 120 to lock can add a significant amount of time to the already lengthy time it takes to lock the DLL 110.
An alternative clock generation circuit placing a DLL in parallel with a DCC is described in U.S. Pat. No. 7,227,809. An embodiment of the parallel configuration is shown in FIG. 2, and the embodiment shown in FIG. 2 improves some of the jitter and slowness concerns of the design shown in FIG. 1. The parallel operation in FIG. 2 is made possible by propagating buffered complementary input signals rCLK and fCLK to both the DLL 300 and DCC circuit 308 as they are generated. The clock generator 302 includes a DLL 300 and a DCC circuit 308, having a divider block 310, and a duty error detection block 320. The DLL 300 includes an input buffer 360, but receives input clock signals CLK and CLK*. The CLK and CLK* signals are complementary clock signals and are shown in the timing diagram of FIG. 3 as not having 50% duty cycles. Buffered clock signals rCLK and fCLK are generated by the input buffer 360 in response to the CLK and CLK* signals.
The DLL 300 includes two delay lines that each corresponds to one of the buffered input signals rCLK and fCLK. The rCLK signal is provided to the adjustable delay 368 to generate a feedback signal fb that is delayed relative to the rCLK signal by an adjustable delay of the adjustable delay line 368. The fb signal is further delayed through a model delay 376 to provide a delayed feedback signal fbdly to the phase detector 380. The phase detector 380 determines the phase difference between the rCLK signal and the fbdly signal and generates a control signal indicative of the phase difference that is provided to the shift register/control circuit 372. Using the control signal, the shift register/control circuit 372 adjusts the delay of the adjustable delay line 368 until the rCLK and fbdly signals are in phase. When this occurs, the DLL 300 is described as obtaining a “locked” state, and the total delay of the fb signal relative to the CLK signal is such that an output clock signal rclk_sync, which is delayed relative to the fb signal by the propagation delay of the output buffer 388, is in phase, or synchronized, with the CLK signal.
The adjustable delay line 364, which provides a delay to the fCLK signal, is adjusted by the shift register/control circuit 372 to have the same delay as the adjustable delay line 368. As a result, the output clock signal fclk_sync is delayed relative to the fCLK signal by the same amount as the rclk_sync signal is delayed relative to the rCLK signal. Thus, the output clock signal fclk_sync is also synchronized with the CLK* signal and the complementary relationship between the rCLK and fCLK signals is maintained by the rclk_sync and fclk_sync signals.
Although the rclk_sync and fclk_sync signals are synchronized with the CLK and CLK* signals, the duty cycle of the rclk_sync and fclk_sync signals is not 50%. The DCC circuit 308 adjusts the delay of the adjustable delay line 364 to provide duty cycle corrected complementary clock signals. That is, although the respective duty cycles of the rclk_sync and fclk_sync signals remain uncorrected, duty cycle error correction is provided by changing the timing of one of the output clock signals relative to the other output clock signal to provide rising clock edges of the output clock signals corresponding to clock edges of a clock signal having a 50% duty cycle.
The duty error correction mechanism includes a divider block 310 and duty error detection block 320. The divider block 310 includes frequency divider circuits 324, 328 for generating three clock signals A, B, and C, having one-half the clock frequency of the rCLK and fCLK signals. The rCLK and fCLK signals are provided to each of the divider circuits 324, 328. The divider circuit 324 receives the rCLK signal at a rising edge input and receives the fCLK signal at a falling edge input. The divider circuit 324 generates the clock signal A by making a clock transition in the clock signals in response to the combination of a rising edge of the rCLK signal and a falling edge of the fCLK signal. The divider circuit 324 further generates the clock signal C, where the signal C is inverse of the signal A. Similarly, the divider circuit 328 generates the clock signal B by making a clock transition in the clock signals in response to a rising edge of the fCLK signal and a falling edge of the rCLK signal.
The duty error detection block 320 then receives the clock signals A, B, and C from the divider block 310. The duty error detection block includes two adjustable delay lines 332, 336, to provide adjustable delays for the clock signals A and B. In one embodiment, each adjustable delay lines 332, 336 is adjustable to provide no more than half of the adjustable delay of delay lines 364, 368 in the DLL 300. Adjustable delay lines having maximum adjustable delays other than approximately one-half the maximum delay of the delay lines 364, 368 can also be used. Using adjustable delay lines of approximately one-half the adjustable delays of the DLL has the benefits of reducing the area occupied by the adjustable delay lines 332, 336. The delay line 332 of the duty error detection block 320 receives and delays the signal A, which is then sent to a phase detector 340. The phase detector 340 receives the signal B and the delayed signal A and generates a signal representing the phase difference of the two signals. Similarly, the delay line 336 of the duty error detection block 320 receives and delays the signal B, which is then sent to a phase detector 344. The phase detector 344 receives the delayed signal B and the signal C and generates a signal representing the phase difference of the two signals. The difference signals from the phase detectors 340, 344 are provided to the adjustable delay lines 332, 336, respectively, to adjust the delay to put the delayed signal A in phase with the signal B and to put the delayed signal B in phase with the signal C. The difference signals from the phase detectors 340, 344 are also provided to the duty error calculator 356 to calculate the delay adjustment necessary to correct the duty cycle error.
The parallel arrangement of the adjustable delay lines 332, 336 of the DCC circuit 308 to the adjustable delay lines 364, 368 of the DLL 300 reduces the clock jitter due to power supply noise and improves the time and power consumption needed to generate a corrected clock signal.
The operation of the duty error calculation in FIG. 2 is illustrated in the timing diagram of FIG. 3. The input clock signals CLK and CLK* are complementary to each other and exhibit a notable distortion in the duty cycle. At the rising edge of the CLK signal, such as at time T0, the rCLK signal transitions high and at the falling edge of the CLK signal, such as at time T1, the rCLK signal transitions low. Similarly, the fCLK signal, which is out of phase by 180° with respect to the rCLK signal, transitions high and low relative to the rising and falling edges of the CLK* signal.
The divider circuit 324 generates the clock signal A having transitions when a rising edge of the rCLK signal crosses a falling edge of the fCLK signal. The signal C is the inverse of the signal A, and is also generated by the divider circuit 324. In contrast, the divider circuit 328 generates the clock signal B having transitions when a rising edge of the fCLK signal crosses a falling edge of the rCLK signal. As a result, the clock signal B generated by the divider circuit 328 has a frequency that is half the frequency of the rCLK and fCLK signals and has a 50% duty cycle.
As shown in FIG. 3, the clock signal B is out of phase relative to the clock signal A by a delay (1) that corresponds to the time the CLK signal is high (and the CLK* signal is low). As further shown in FIG. 3, the clock signal C is out of phase relative to the clock signal B by a delay (2) that corresponds to the time the CLK* signal is high (and the CLK signal is low). The delays (1) and (2) are indicative of the duty cycle distortion in the CLK and CLK* signals, and exhibited in the rCLK and fCLK signals. As a result, the delays (1) and (2) can be used to calculate a duty cycle error from a desired 50% duty cycle. More specifically, the duty cycle error is equal to (|(1)−(2)|)/2. The delays (1) and (2) are measured using the delay lines 332, 336 and the phase detectors 340, 344. To measure the delay (1), delayed signal A (not shown) is compared to the clock signal B by the phase detector 340. The phase detector 340 will adjust the adjustable delay line 332 until the delayed signal A is in phase with the clock signal B, that is the rising edges of the delayed signal A and the clock signal B are aligned. Consequently, when the signals are in phase, the control signal output by the phase detector 340 to set the delay of the adjustable delay line 332 is indicative of the delay (1). Similarly, to measure the delay (2), the phase detector 344 compares the delayed signal B (not shown) to signal C. As with the phase detector 340 and the adjustable delay line 332, when the adjustable delay line 336 is adjusted by the phase detector 344 so that the delay signal B and the clock signal C are in phase, the control signal output by the phase detector 344 is indicative of the delay (2). The control signals output by the phase detectors 340, 344 are provided to the duty error calculator 356. As previously discussed, the correction for achieving a 50% duty cycle can be determined by calculating half the difference between the delays (1) and (2). This calculation is conducted by the duty error calculator 356.
In summary, FIG. 1 depicts a clock generating circuit having series-connected DLL and DCC circuitry. The design in FIG. 1 suffers from the problems of clock jitter, excessive power consumption and slow time to complete locking. The design in FIG. 2 improves on FIG. 1 by placing the DLL and DCC circuitry in parallel. However, the design in FIG. 2 utilizes open-loop duty-cycle correction. Duty cycle error can be unacceptably accumulated in the design of FIG. 2 and any duty cycle error introduced by the DCC circuit itself goes uncorrected by the clock generator of FIG. 2.
Accordingly, still further improved clock generation would be desirable.